Cascade Lake(CSL / CLX)是Intel继Skylake之后的继任者,Skylake是面向发烧友和服务器的14 nm微体系结构。 Cascade Lake是英特尔PAO模型的一部分,处于“优化”阶段。
对于台式机爱好者来说,Cascade Lake是品牌的Core i7和Core i9处理器(在Core X系列下)。 对于可扩展的服务器级处理器,英特尔将其品牌命名为Xeon Bronze,Xeon Silver,Xeon Gold和Xeon Platinum。
用途
内核 | 简写 | 平台 | 终端市场 |
---|---|---|---|
Cascade Lake X | CSL-X | Glacier Falls | 桌面 |
Cascade Lake W | CSL-W | 企业级工作站 | |
Cascade Lake SP | CLX-SP | Purley | 可调节式服务器 |
Cascade Lake AP | CLX-AP | 先进服务器 |
品牌
Cascade Lake 有五个品牌
Logo | Family | General Description | Differentiating Features | |||||||
---|---|---|---|---|---|---|---|---|---|---|
Cores | HT | TBT | AVX-512 | AVX-512 Units | UPI links | Scalability | ||||
Xeon W | High-performance Workstations | 8-28 | ✔ | ✔ | ✔ | 1 | – | – | ||
Xeon Bronze | Entry-level performance / Cost-sensitive |
6 | ✘ | ✘ | ✔ | 1 | 2 | Up to 2 | ||
Xeon Silver | Mid-range performance / Efficient lower power |
8-16 | ✔ | ✔ | ✔ | 1 | 2 | Up to 2 | ||
Xeon Gold 5000 | High performance | 4-18 | ✔ | ✔ | ✔ | 1 | 2 | Up to 4 | ||
Xeon Gold 6000 | Higher performance | 8-24 | ✔ | ✔ | ✔ | 2 | 3 | Up to 4 | ||
Xeon Platinum | Highest performance / flexibility | 4-28 | ✔ | ✔ | ✔ | 2 | 3 | Up to 8 |
Identification[edit]
Where,
- “F” suffix integrates the Omni-Path Host Fabric Interface (HFI) die on-package
- “L” suffix indicates the SKU is a large memory (4.5 TiB) tier SKU
- “M” suffix indicates the SKU is a medium memory (2 TiB) tier SKU
- “N” suffix indicates the SKU is a networking-specialized model
- “S” suffix indicates the SKU is a search application-specialized model
- “T” suffix indicates that SKU has an extended lifetime (10 year use) guarantees and NEBS-friendly packing specification
- “U” suffix indicates the SKU is a single-socket model (even if part of the Xeon Gold family that normally supports up two 4-way SMP)
- “V” suffix indicates the SKU targets the VM density value market
- “Y” suffix indicates the SKU has Speed Select Technology (SST)
Note that Speed Select (SST) SKUs were originally suffixed with the ‘C’ suffix but were later changed to ‘Y’. Some of the early engineering samples that are circulating around still suffixed with a ‘C’.
更多请参考:
https://en.wikichip.org/wiki/intel/microarchitectures/cascade_lake